Successive approximation analog to digital converters (ADCs) are designed to use N clock cycles (typically generated by an external clock) to convert an analog signal to a set of N digital bits. Recently, there is a desire to improve the performance of such successive approximation ADCs using enhanced error correction techniques such as digital error correction (DEC) and mismatch error correction (MEC). Performing enhanced error correction techniques may require the usage of additional clock cycles beyond the N cycles available via a standard external clock.